The present invention relates generally to clock and data recovery (CDR) systems and more specifically to improving interpolator linearity in CDR systems.
Clock and data recovery (CDR) operations are performed in many communication circuits. Digital communication receivers sample an analog waveform and then detect the data that the waveform represents. The phase of the analog waveform is typically unknown and there may be a frequency offset between the frequency at which the original data was transmitted and the nominal receiver sampling clock frequency. The CDR function is used to properly sample an analog waveform using a reference clock to correctly recover the data.
FIG. 1 shows a block diagram of a prior art CDR circuit 100. The CDR circuit 100 receives as input a reference clock 140 and an analog data stream 104 that represents digital bits (i.e., 1s and 0s), and provides as output a recovered clock 110 and recovered data 106. The data stream 104 is often a differential waveform as represented by waveform 108. The differential waveform 108 has multiple so-called “eyes” 112 which represent the maximum and minimum amplitude of the data stream 104 during a time interval. The waveform 108 has transition points, such as transition points 120, 124, that indicate the transition from one eye to the next. Each eye also has a respective midpoint (e.g., midpoint 116 of eye 112).
The CDR circuit 100 includes a series of latches 134 that are clocked from a clock signal 126 to sample the data stream 104 at the midpoint 116 of the eye 112. The midpoint 116 of the eye 112 is typically sampled because the CDR circuit often has the best chance of correctly identifying whether the waveform is representing a digital 0 or a digital 1 at that instant in time. The CDR circuit 100 determines each transition point (e.g., transition point 120 and 124) and the midpoint 116 of the eye 112.
Due to imperfections and nonlinearities in the transmission device or transmission medium, or offset between the transmit and receive frequencies, the data signal may shift in time during the transmission relative to the clock signal. This shifting in time may result in the differential waveform 108 moving (back and forth or in one direction over time with respect to the reference clock 140) as it is being received by the CDR circuit 100.
The CDR circuit 100 determines this time shifting in order to ensure that the CDR circuit 100 samples each eye 112 of the waveform 108 at its midpoint 116. The CDR circuit 100 determines the transition point 120 and 124 and midpoint 116 of each eye 112 and then changes the phase of an output signal 126 of an interpolator 128 of the CDR circuit 100, via a control signal 130. The CDR circuit 100 samples the input data stream 104 at points determined by the phase of the output signal 126 of the interpolator.
To change the phase of the output signal 126, input clock signal 140 is delayed, creating a new clock signal 144. These clock phases are connected to each input 132, 136 of the interpolator 128. In other words, one input clock signal 144 is delayed with respect to the other input clock signal 140. These two input signals provide the minimum phase and the maximum phase for the interpolator 128.
As the phase of the interpolator 128 is changed, however, the input impedance of each input 132, 136 of the interpolator 128 also changes. This variation in input impedance results in an amplitude variation of the input clock signals 140, 144. This, in turn, results in an undesirable change in the phase of the input clock signals 140, 144 relative to each other.
Thus, the prior art interpolator (and, therefore, CDR circuit) does not change phases in a smooth, linear manner. Instead, the phase of the prior art interpolator's output signal 126 changes as a result of an impedance variation with respect to the interpolator's inputs. As a result, the input data stream 104 may not be sampled correctly.